Shop Talk

Will SpaceX Reach 150 Launches in 2026? Prediction Market & Cadence Forecast

Will SpaceX Reach 150 Launches in 2026? Prediction Market & Cadence Forecast

David Rogers
2026-08-17

An analytical forecast of SpaceX's 2026 launch cadence, validating prediction market strike prices (120, 140, 150+) against pad capacity and weather risks.

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Thermal Interface Materials (TIMs) Heat Dissipation in Scaling AI Infrastructure

David Rogers
2026-08-14

Discover how advanced Thermal Interface Materials (TIMs)—spanning liquid metals, vertically aligned graphene, and polymer composites—bridge critical thermal bottlenecks, sustain 1kW-class AI GPUs, and navigate supply chain risks.

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Thermal Interface Materials (TIMs) Heat Dissipation in Scaling AI Infrastructure
Glass Core Substrates & Interposers: The Future of AI Chip Packaging

Glass Core Substrates & Interposers: The Future of AI Chip Packaging

David Rogers
2026-08-13

Discover how glass core substrates and TGVs enable 10x interconnect density, reduce signal loss, and solve thermal warpage in next-gen AI and HPC packages.

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FC-BGA Substrates & ABF: Process, Supply Constraints, and AI Market Drivers

David Rogers
2026-08-12

An engineer’s guide to FC-BGA substrates, ABF material properties, and thermal warpage challenges driving AI silicon, glass cores, and global supply tightness.

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FC-BGA Substrates & ABF: Process, Supply Constraints, and AI Market Drivers
HBM Stacking & Packaging Explained: Architecture, Yields, & Market Outlook

HBM Stacking & Packaging Explained: Architecture, Yields, & Market Outlook

David Rogers
2026-08-11

Explore High-Bandwidth Memory (HBM) stacking architecture, MR-MUF vs. TCB-NCF packaging, HBM4 yield updates, and global supply chain dependencies.

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Why TSMC’s CoWoS and SoIC Advanced Packaging Bottleneck Global AI Accelerator Output

David Rogers
2026-08-10

An in-depth technical look at TSMC's CoWoS and SoIC advanced packaging, exploring hybrid bonding, thermal warpage, yield limits, and supply projections through 2027.

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Why TSMC’s CoWoS and SoIC Advanced Packaging Bottleneck Global AI Accelerator Output
The Silicon Bottleneck: How Mature Nodes Power the AI Infrastructure Boom

The Silicon Bottleneck: How Mature Nodes Power the AI Infrastructure Boom

David Rogers
2026-08-07

Uncover how mature and specialty nodes (28nm+) are driving the AI expansion. Learn how BCD technology, PMICs, and supply constraints impact AI power delivery.

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3nm and 2nm Foundry Nodes: EUV, GAA Transistors, and AI Silicon Trends

David Rogers
2026-08-06

Explore the technology driving 3nm and 2nm logic foundries: EUV lithography, GAA nanosheets, backside power delivery, and AI hardware capacity constraints.

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3nm and 2nm Foundry Nodes: EUV, GAA Transistors, and AI Silicon Trends
Compound Semiconductors Explained: GaN, SiC, and InP in the AI & EV Era

Compound Semiconductors Explained: GaN, SiC, and InP in the AI & EV Era

David Rogers
2026-08-05

Explore how GaN, SiC, and InP foundries power AI data centers, EVs, and 800G/1.6T optics, overcoming substrate supply risks and scaling to 200mm wafers.

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Inside Compound Semiconductor MOCVD: Technology, Markets, and Supply Chain Constraints

David Rogers
2026-08-04

Explore how MOCVD drives GaN and InP compound semiconductor production. Learn about epitaxial growth mechanics, market trends in AI optics, and supply constraints.

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Inside Compound Semiconductor MOCVD: Technology, Markets, and Supply Chain Constraints