The Silicon Bottleneck: How Mature Nodes Power the AI Infrastructure Boom
- David Rogers
- AI Buildout Supply Chain
- 2026-08-07
NEED TO KNOW
- The AI Backbone Runs on Legacy Silicon: While advanced nodes focus on digital compute, mature and specialty nodes (28 nm and above, on 200 mm/300 mm wafers) supply the indispensable power management ICs (PMICs), gate drivers, and isolators required to power AI systems.
- BCD Technology Enables Single-Chip Power Systems: Bipolar-CMOS-DMOS (BCD) technology combines low-voltage digital control, high-voltage power switching (LDMOS), and precision analog functions onto a single die, enabling highly integrated power regulation.
- Process Complexity Differs from Moore's Law: Analog manufacturing relies on precision matching, thick/thin gate oxide integration, and deep-trench isolation (DTI) rather than sub-nanometer extreme ultraviolet (EUV) lithography scaling.
- Capacity Squeeze and Geopolitical Realignment: Foundry capacity reallocations to interposers and high-margin PMICs are driving fab utilization toward ~90%, while China expands its legacy footprint (target ~45% global mature capacity by 2027) alongside 300 mm expansions by US IDMs like Texas Instruments.
Specialty and mature nodes, typically 28 nanometers (nm) and larger, often built on 200 millimeter (mm) and 300 mm silicon wafers, form the critical backbone of the AI buildout. Unlike advanced digital logic that scales to increase transistor density, analog and mixed-signal circuits prioritize signal precision, low noise, high-voltage control, and circuit isolation. The primary manufacturing technology is Bipolar-CMOS-DMOS (BCD). BCD combines low-voltage digital CMOS logic, high-voltage Lateral DMOS power switches, and precision analog components on one chip /ST/. This integration enables power-management integrated circuits (PMICs), voltage regulators, gate drivers, and isolators to convert and deliver stable power to AI accelerators. Process complexity comes from balancing thick gate oxides for high voltages with thin gate oxides for digital logic, creating deep-trench isolation to separate circuit domains, and integrating passive components. These requirements do not improve with traditional scaling and require stable, well-characterized process flows rather than extreme ultraviolet (EUV) lithography.
AI data-center power density is now the main demand driver. As equipment racks scale toward hundreds of kilowatts and eventually megawatt-class systems, analog content per rack rises sharply to support multi-phase voltage regulation, intermediate bus converters, sensors, and circuit protection. Analysts project the market for analog semiconductors in AI data centers to grow from roughly $7.9 billion in 2025 to $27 billion by 2030—a ~28% annual growth rate—outpacing the general analog market. This demand, combined with automotive, industrial, and edge-AI needs, creates severe supply constraints.
Fab capacity is tightening rather than expanding smoothly. Leading foundries have reduced 200 mm wafer output and moved 300 mm mature capacity toward higher-margin AI products, such as PMICs, power discretes, and silicon interposers. This shift pushes fab utilization toward 90% and causes price increases expected to extend into 2027 /Taipei Times/. China is building a larger share of global mature-node capacity that is projected to approach 45% by 2027 through expansion at SMIC, Hua Hong, and other foundries, while taking overflow orders for high-voltage and lower-margin chips. Texas Instruments is countering this trend by expanding 300 mm analog capacity in Texas /EETimes/ and Utah to lower production costs and increase supply chain security. Wafer reclaim works at higher success rates on mature nodes than on advanced nodes /Mordor Intelligence/, and companies recycle limited power components, but neither practice solves core factory capacity limits.
Key process and product companies include Texas Instruments, Analog Devices, Infineon, STMicroelectronics, and Onsemi on the integrated design and manufacturing side. Foundry capacity is concentrated at GlobalFoundries, UMC, TSMC’s mature lines, SMIC, and Hua Hong. In South Korea, DB HiTek remains a vital pure-play 200 mm foundry, supplying specialized PMICs and high-voltage power components /PR Newswire/. Regional concentration remains a risk: Taiwan holds critical specialty process expertise even as it expands advanced nodes, while China’s rapid mature-node expansion creates both additional supply and supply-chain division risks for international customers. The result is a supply squeeze in the hardware layer that keeps AI systems powered and operational.
Key Insights
What capacity estimates and mature wafer volumes are required to power next-generation AI architectures like NVIDIA’s Vera Rubin NVL72?
Next-generation AI supercomputing racks like the NVIDIA Vera Rubin NVL72 demand between 190 kW and 230 kW per rack—scaling toward 600 kW for Rubin Ultra systems—requiring hundreds of multi-phase voltage regulators, Smart Power Stages (SPS), gate drivers, and point-of-load (PoL) converters per rack. Supporting projected deployment volumes of thousands of rack-scale platforms per year translates into tens of millions of discrete power management ICs. This creates a demand footprint of tens of thousands of dedicated 200 mm and 300 mm BCD wafer starts per year strictly for power delivery and telemetry.
How do China’s rapid mature-node expansion and historical semiconductor cyclicality threaten global market stability for power and analog chips?
Driven by aggressive state subsidies and domestic localization mandates, Chinese foundries led by SMIC, Hua Hong, Nexchip, and GTA Semiconductor are rapidly expanding mature-node capacity, targeting up to 40–45% of global legacy output. Historically, uncoordinated capital expenditure waves in legacy nodes trigger severe bullwhip cycles, leading to structural overcapacity, inventory gluts, and price erosion once demand surges cool. However, because complex power and analog components require stringent multi-year qualification, high-reliability BCD process engineering, and strict supply chain resilience, the market is bifurcating rather than collapsing into a unified price war. While commodity power discretes and low-tier analog ICs face intense downward pricing pressure from Chinese overcapacity, high-reliability AI data-center power platforms remain largely insulated, locking in premium margins for qualified Western IDMs and specialty foundries.
What is the most critical process technology bottleneck in AI power delivery, and why can it not be scaled down?
Bipolar-CMOS-DMOS (BCD) process technology operating on 40 nm to 180 nm mature nodes represents the primary structural bottleneck in AI hardware expansion. Unlike digital logic, BCD cannot be shrunk using sub-nanometer extreme ultraviolet (EUV) lithography because high-voltage Lateral DMOS (LDMOS) power transistors require thick gate oxides and wider physical drift regions to withstand elevated operational voltages without dielectric breakdown. Integrating low-voltage CMOS control logic, precision analog reference circuits, and high-voltage power switches on a single die relies on deep-trench isolation and stable, highly specialized process characterization rather than physical feature-size scaling.
How are the unit economics, margin defensibility, and supply dynamics of mature-node power components evolving for AI infrastructure?
High-voltage BCD power components command defensible unit economics and gross margins often exceeding 50% due to steep qualification barriers, specialized process engineering, and high customer switching costs. With mature-node fab utilization rates pushing toward 90%, hyperscalers and Tier-1 server OEMs are mitigating supply risk by entering multi-year Long-Term Supply Agreements (LTSAs) with non-cancelable volume commitments. This structural shift cushions analog IDMs and legacy foundries against traditional semiconductor cyclicality, locking in sustained pricing power and high-margin revenue through the end of the decade.