Understanding Semiconductor Etch Machinery: Dry vs. Wet Processes in Advanced Chipmaking
- David Rogers
- AI Buildout Supply Chain
- 2026-07-24
NEED TO KNOW
- Dry vs. Wet Etch Fundamentals: Dry plasma etching (RIE, ICP) provides directional, vertical cuts for high-aspect-ratio structures like 3D NAND and GAA nanosheets, while wet chemical etching offers isotropic removal suited for confined spaces like SiGe sacrificial layer release.
- Nanometer-Scale Challenges: Shrinking feature sizes below 2nm cause aspect-ratio-dependent etching (ARDE), profile bowing, and stiction, driving adoption of cryogenic plasma, pulsed RF sources, and AI digital twin recipe modeling.
- Equipment Market Growth: Driven by AI chips and HBM demand, the semiconductor etch equipment market is projected to grow from ~25B in 2025 to 35–$40B by 2030–2031, with dry etch accounting for ~90% of revenue.
- Market Leaders: Global dry and conductor etch manufacturing is dominated by Lam Research, Applied Materials, and Tokyo Electron, with SCREEN holding a strong position in wet processing.
- Supply Chain Risks: The sector faces a dual geopolitical bottleneck: western export controls on advanced dry plasma tools, and China’s control over ~60%+ of global fluorspar feedstock required for hydrofluoric acid reagents.
In AI semiconductor fabrication, chipmakers are faced with a monumental challenge: carving out intricate three-dimensional features on a scale measured in angstroms (one ten-billionth of a meter) /sk hynix/. At the heart of this atomic sculpting are two distinct machinery methods: dry plasma etching and wet chemical etching.
Plasma etch, dominated by reactive ion etching and inductively coupled plasma systems, acts as the industry’s precision laser. By energizing gases into a plasma state, these tools blast ionized particles straight down into a wafer to achieve strict vertical, directional cuts. This capability is non-negotiable for the towering vertical architecture of modern chips, such as 3D NAND memory cells with depth-to-width ratios that exceed one hundred to one /Phys/, or the delicate vertical channels of Gate-All-Around nanosheets.
Wet etch, by contrast, takes a gentler approach. Using ultra-pure liquid acid baths, it dissolves target materials uniformly in all directions. While it lacks the directional control of plasma, wet etching shines in tight, enclosed spaces. It is essential for selectively clearing out tiny sacrificial layers within nanosheet stacks or shaping work-function metals, doing so without damaging surrounding layers. Both methods demand near-impossible levels of chemical purity where even a single part-per-billion of metal impurity can ruin a chip, and rely on atomic layer etching techniques to remove material practically one atom at a time.
Yet, pushing chip design to two nanometers and beyond creates severe physical bottlenecks. Deep plasma cuts often suffer from depth loading, where the etch rate slows down the deeper the trench goes, leading to profile defects where holes twist, bow, or pinch shut. On the liquid side, wet etching must constantly fight capillary forces that threaten to pull microscopic nanosheets together and ruin the structure. To solve this, the industry is turning to high-tech remedies. Cryogenic plasma etching uses super-cooled chemical reactions to boost etch speeds up to a hundredfold while using lower-emission gases /Nagoya University/. Meanwhile, ultrafast pulsed radio-frequency power sources allow tools to adjust plasma characteristics in real time /EHT Semi/, and AI-driven digital twins simulate complex chemical recipes in software before a single physical wafer is touched.
This technological revolution is fueling massive financial growth, driven by the explosive demand for advanced artificial intelligence hardware, high-bandwidth memory (HBM), and ultra-dense storage chips. The semiconductor etch equipment market, valued at ~$25 billion in 2025 is projected to expand to ~$40 billion by 2031 /Mordor Intelligence/. Momentum stems from the sharp rise in etch steps needed for sub-3 nm logic, the transition to gate-all-around transistors, the vertical scaling of 300-plus-layer NAND, and high-bandwidth memory stacks that demand through-silicon vias /EI/ with aspect ratios above 100:1. Memory applications already accounted for nearly 40% of 2025 revenue, while advanced packaging and HBM are expected to grow even faster, underscoring etch’s critical role in enabling denser, higher-performance AI silicon.
Despite this economic momentum, the industry sits on fragile geopolitical ground. Tool manufacturing is dominated by a tight oligopoly led by Lam Research, Tokyo Electron, and Applied Materials, alongside specialized players like SCREEN, Hitachi High-Tech, and emerging Chinese manufacturers like AMEC and NAURA. This concentration creates a delicate dual bottleneck for global chip production. On one side, advanced plasma tools remain tightly controlled by American and Japanese firms subject to strict export restrictions /CNBC/. On the other, the raw chemical supply chain remains heavily reliant on fluorspar /EI/, the key feedstock for hydrofluoric acid used in both wet and dry processes, over sixty percent of which is mined in China. Because extreme chip purity requirements make gas recycling economically difficult, the global buildout of next-generation AI hardware remains deeply vulnerable to both high-tech equipment controls and raw material trade friction.
Key Insights
How many dry etch tools are deployed in leading-edge foundries like TSMC N2 or Intel 14A?
The transition to gate-all-around (GAA) nanosheets and backside power delivery at advanced sub-2nm nodes like TSMC N2 and Intel 14A increases etch process intensity by over 20%, requiring high-volume gigafabs to deploy hundreds of specialized dry etch chambers per 100,000 wafer-starts-per-month (WSPM) capacity. Major vendors like Lam Research maintain a global active installed base exceeding 90,000 chambers across logic, foundry, and memory fabs, with leading-edge nodes driving accelerated tool upgrades and new system installations to handle complex multi-patterning and atomic-layer etching workloads.
What is the most critical process bottleneck in modern semiconductor etch technology?
The defining process bottleneck in advanced etch technology is high-aspect-ratio (HAR) etching, where tools must carve deep vertical features exceeding 50:1 to 100:1 aspect ratios for 3D NAND memory holes and GAA channel releases without causing profile defects like bowing, necking, or twisting. Aspect-ratio-dependent etching (ARDE) restricts reactant gas delivery and byproduct removal at extreme depths, slowing material removal rates and degrading yield, which makes atomic layer etching (ALE) precision and pulsed RF energy control the ultimate limiting factors for sub-2nm chip manufacturing.
What are the unit economics, cyclicality, and margin defensibility of etch equipment manufacturers?
Etch machinery manufacturers operate with strong pricing power and high gross margins (~50%), defended by immense research and development barriers to entry and intimate co-development relationships with leading chipmakers. While tool shipment volumes remain tied to semiconductor capital expenditure cycles, suppliers mitigate cyclicality through long-term service agreements and high-margin recurring revenue from spare parts, software optimization, and chamber refurbishments—an installed-base support business that accounts for over a third of total revenue and provides resilient cash flow throughout industry downturns.